CMOS or CCD image sensors are of interest in a wide variety of sensing and imaging applications in a wide range of fields including consumer, commercial, industrial, and space electronics. Imagers based on charge coupled devices (CCDs) are currently the most widely utilized. CCDs are employed either in front or back illuminated configurations. Front illuminated CCD imagers are cost effective to manufacture compared to back illuminated CCD imagers such that front illuminated devices dominate the consumer imaging market. Front side illumination, while traditionally utilized in standard imagers, has significant performance limitations such as low fill factor/low sensitivity. The problem of low fill factor/low sensitivity is typically due to shadowing caused by the presence of opaque metal bus lines, and absorption by the array circuitry structure formed on the front surface in the pixel region. Thus, the active region of the pixel is typically very small (low fill factor) in large format (high-resolution) front illuminated imagers.
Thinned, back illuminated, semiconductor imaging devices are advantageous over front-illuminated imagers for high fill factor, better overall efficiency of charge carrier generation and collection, and are suitable for small pixel arrays. One goal of the performance of back illuminated, semiconductor imaging devices is that the charge carriers generated by light or other emanation incident on the backside should be driven to the front side quickly to avoid any horizontal drift, which may smear the image. It is also desirable to minimize the recombination of the generated carriers before they reach the front side, since such recombination reduces overall efficiency and sensitivity of the device.
These desires may be achieved by providing a thin semiconductor layer and a high electric field within this layer. The field should extend to the back surface, so that the generated carriers, such as electrons or holes, can be driven quickly to the front side. This requires additional treatment at the backside of the device, which adds to the complexity of the fabrication process. One current technique includes chemical thinning of semiconductor wafers and deposition of a “flash gate” at the backside after thinning. This requires critical thickness control of the backside flash gate. Another technique involves growth of a thin dopant layer on a wafer back using molecular beam epitaxy (MBE). Still another known method used to provide a desired electric field is to create a gradient of doping inside the thinned semiconductor layer by backside implant of the layer followed by appropriate heat treatment for annealing and activation. These methods can not be easily included in conventional semiconductor foundry processing, and require more expensive custom processing.
Fabrication of thinned back-illuminated imagers has other challenges: For example, thinned back illuminated imagers can have inherent dangling bonds present at the silicon back surface, which may cause generated electrons to recombine at the back surface. Therefore, quantum efficiency (QE) can be degraded if the backside of the thinned imager is not treated to reduce traps. Thinning of wafers poses yield issues such as stress in the thinned wafer due to non-uniformity of epitaxial layer thickness. For these and the above reasons, fabrication cost is much higher for high volume production of back-illuminated imagers than for front illuminated imagers.
A cost effective process for manufacturing silicon-on-insulator (SOI) based back illuminated CCD/CMOS imagers is proposed in co-pending, commonly owned U.S. patent application Ser. No. 11/350,546, the disclosure of which is incorporated herein by reference in its entirety. The fabrication method proposed in that application not only solves the above mentioned problems, but also had several advantages over other proposals for back illuminated CCD/CMOS imagers, including:                The proposed method is fully compatible with existing CCD/CMOS imager foundry processes.        The proposed method has no need for any special backside treatment.        The buried oxide layer of the SOI wafers acts as a natural stopping layer for a high throughput thinning process.        The thickness of epitaxial layer grown using this process is precisely controlled. This, in conjunction with the natural stopping oxide insulating layer of the SOI, can result in highly uniform thickness as compared to conventional approaches.        The proposed method allows for multi-level metal processing.        Devices manufactured using the proposed method can be fully tested before applying the steps of wafer thinning/lamination, which results in major cost reductions in a production environment.        
Some imaging systems incorporate color filters and micro-lenses into the image sensors to produce wavelength dependent signals. To date, this has been done mostly with front illuminated imagers. Fabrication of color filters and micro-lens for thinned back illuminated imagers, even for the method proposed above, is a complex process. Alignment of color filters/micro-lenses on the backside to the pixels in the front side is very critical. Back to front alignment is possible, but with less degree of alignment accuracy. Apart from that, wire bonding and packaging of such back thinned imagers with color filters and micro-lenses add to complexity of the process.
Accordingly, what would be desirable, but has not yet been provided, is a device and method for fabricating back illuminated imagers which can cost-effectively incorporate color filters, micro-lenses, and wire bonding techniques.